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  • Produktbild: Data Converters
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Data Converters

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112,99 € UVP 128,39 €

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Beschreibung

Produktdetails

Einband

Gebundene Ausgabe

Erscheinungsdatum

22.02.2007

Verlag

Springer Us

Seitenzahl

440

Maße (L/B/H)

24,1/16/3,3 cm

Gewicht

936 g

Auflage

2007

Sprache

Englisch

ISBN

978-0-387-32485-2

Beschreibung

Produktdetails

Einband

Gebundene Ausgabe

Erscheinungsdatum

22.02.2007

Verlag

Springer Us

Seitenzahl

440

Maße (L/B/H)

24,1/16/3,3 cm

Gewicht

936 g

Auflage

2007

Sprache

Englisch

ISBN

978-0-387-32485-2

Herstelleradresse

Springer-Verlag KG
Sachsenplatz 4-6
1201 Wien
AT

Email: [email protected]

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  • Produktbild: Data Converters
  • Produktbild: Data Converters
  • 1. BACKGROUND ELEMENTS. 1.1 The Ideal Data Converter. 1.2 The Sampling. 1.2.1 Undersampling. 1.2.2 Sampling-time Jitter. 1.3 Amplitude Quantization. 1.3.1 Quantization Noise. 1.3.2 Properties of the Quantization Noise. 1.4 kT/C Noise. 1.5 Discrete and Fast Fourier Transforms. 1.5.1 Windowing. 1.6 Coding Schemes. 1.7 The D/A Converter. 1.7.1 Ideal Reconstruction. 1.7.2 Real Reconstruction. 1.8 The z-Transform. References. 2. DATA CONVERTERS SPECIFICATIONS. 2.1 Type of Converter. 2.2 Conditions of Operation. 2.3 Converter Specifications. 2.3.1 General Features. 2.4 Static Specifications. 2.5 Dynamic Specifications. 2.6 Digital and Switching Specifications. References. 3. NYQUIST-RATE D/A CONVERTERS. 3.1 Introduction. 3.1.1 DAC Applications. 3.1.2 Voltage and Current References. 3.2 Types of Converters. 3.3 Resistor based Architectures. 3.3.1 Resistive Divider. 3.3.2 X-Y Selection. 3.3.3 Settling of the Output Voltage. 3.3.4 Segmented Architectures. 3.3.5 Effect of the Mismatch. 3.3.6 Trimming and Calibration. 3.3.7 Digital Potentiometer. 3.3.8 R-2R Resistor Ladder DAC. 3.3.9 Deglitching. 3.4 Capacitor Based Architectures. 3.4.1 Capacitive Divider DAC. 3.4.2 Capacitive MDAC. 3.4.3 'Flip Around' MDAC. 3.4.4 Hybrid Capacitive-Resistive DACs. 3.5 Current Source based Architectures. 3.5.1 Basic Operation. 3.5.2 Unity Current Generator. 3.5.3 Random Mismatch Unary Selection. 3.5.4 Current Sources Selection. 3.5.5 Current Switching and Segmentation. 3.5.6 Switching of Current Sources. 3.6 Other Architectures. References. 4. NYQUIST RATE A/D CONVERTERS. 4.1 Introduction. 4.2 Timing Accuracy. 4.2.1 Metastability error. 4.3 Full-Flash Converters. 4.3.1 Reference Voltages. 4.3.2 Offset of Comparators. 4.3.3 Offset Auto-zeroing. 4.3.4 Practical Limits. 4.4 Subranging and Two-Step Converters. 4.4.1 Accuracy requirements. 4.4.2 Two-step Converter as a Non-linear Process. 4.5 Folding Technique and Interpolation. 4.5.1 Double Folding. 4.5.2 Interpolation. 4.5.3 Use of Interpolation in Flash Converters. 4.5.4 Use of Interpolation in Folding Architectures. 4.5.5 Interpolation for Improving Linearity. 4.6 Time-Interleaved Converters. 4.6.1 Accuracy requirements. 4.7 Successive Approximation Converter. 4.7.1 Errors and Error Correction. 4.8 Pipeline Converters. 4.8.1 Accuracy Requirements. 4.8.2 Digital Correction. 4.8.3 Dynamic Performances. 4.8.4 Sampled-data Residue Generator. 4.9 Other Architectures. 4.9.1 Cyclic (or Algorithmic) Converter. 4.9.2 Integrating Converter. 4.9.3 Voltage-to-Frequency Converter. References. 5. CIRCUITS FOR DATA CONVERTERS. 5.1 Sample-and-Hold. 5.2 Diode Bridge S&H. 5.2.1 Diode Bridge Imperfections. 5.2.2 Improved Diode Bridge. 5.3 Switched Emitter Follower. 5.3.1 Circuit Implementation. 5.3.2 Complementary Bipolar S&H. 5.4 Features of S&H made by BJT. 5.5 CMOS Sample-and-Hold. 5.5.1 Clock Feedthrough. 5.5.2 Clock Feedthrough Compensation. 5.5.3 Two-stages OTA as T&H. 5.5.4 Use of the Virtual Ground in CMOS S&H. 5.5.5 Noise Analysis. 5.6 CMOS Switch with Low Supply Voltage. 5.6.1 Switch Bootstrapping. 5.7 Folding Amplifiers. 5.7.1 Current-Folding. 5.7.2 Voltage Folding. 5.8 Voltage-to-Current Converter. 5.9 Clock Generation. References. 6. OVERSAMPLING DATA CONVERTERS. 6.1 Introduction. 6.1.1 Delta and Sigma-Delta Modulation. 6.2 First and Second Order Sigma-Delta Modulators. 6.2.1 Intuitive Views. 6.2.2 Use of 1-bit Quantization. 6.2.3 Second Order Modulator. 6.2.4 Quantization Error and Dithering. 6.3 High Order Noise Shaping. 6.3.1 Dynamic Range Considerations. 6.3.2 Dynamic Ranges Optimization. 6.4 Practical Considerations. 6.4.1 Offset. 6.4.2 Finite Op-Amp Gain. 6.4.3 Finite Op-Amp Bandwidth. 6.4.4 Finite Op-Amp Slew-Rate. 6.4.5 Noise Considerations. 6.4.6 ADC Non-idealities. 6.4.7 DAC Non-idealities. 6.4.8 Single-bit and Multi-bit. 6.4.9 SNR Enhancement. 6.5 High Order Architectures. 6.5.1 Use of Weighted Feedback Summation. 6.5.2 Use of Local